1. Field of the Invention
Example embodiments of the present invention are directed generally to a calibration circuit and method thereof, and more particular to a calibration circuit including at least one common-mode feedback circuit and method thereof.
2. Description of the Related Art
A degree of linearity in Super Heterydyne systems may be represented by a third order intercept point (IP3). When input signals including two or more frequency components are applied to a conventional non-linear system or circuit, other frequency components may be generated due to non-linearity and/or input frequency components. These additional frequency components may be referred to as Intermodulation (IM), and IM distortion (IMD) may refer to distortion due to the IM components. When the two or more input frequency components are passed through the non-linear system/circuit, various output frequency components may be generated (e.g., a sum of harmonics and/or a difference of harmonics with random coefficients as well as the input frequency components may be generated), which may interfere with a modulation process and/or a demodulation process.
A conventional direct-conversion receiver (DCR) may not convert a carrier frequency signal into an intermediate frequency. Instead, a frequency mixer of the DCR may directly convert a carrier frequency signal into a base-band signal, and a second-order intermodulation distortion (IMD2) may approximate the frequency of the base-band signal. The DCR may thereby be more affected by the IMD2 as compared to a third-order intermodulation distortion (IMD3). Thus, distortion of signal waveforms may generally be adjusted (e.g., reduced) by controlling the IMD2.
A degree of interference due to the IMD2 may be represented by a second-order Intercept Point (IP2) value. The IP2 value may represent a degree of linearity of a conventional DCR system and may thereby be a factor in the performance of communication systems.
A power level of an initial IMD2 may be relatively low. However, the power level of the initial IMD2 may increase (e.g., at a higher rate) to be substantially equal to the power level of an input signal as a power level of the input signal increases. A point at which the power level of the IMD2 equals the power level of the original signal may be referred to as the IP2. In order to enhance the linearity in conventional communication systems, the IP2 value may be set to higher values so as to reduce the IMD2.
FIG. 1 is a circuit diagram illustrating a conventional IP2 calibration circuit 100. Referring to FIG. 1, the IP2 calibration circuit 100 may include a mixer 10 and an IP2 controller 20. The mixer 10 may include a first input terminal pair 2 where a radio frequency input signal VRF may be received and a second input terminal pair 4 where an output signal VLO of a local oscillator (not shown) may be received.
The mixer 10 may output a signal having a frequency corresponding to a difference between a frequency of the radio frequency input signal VRF and a frequency of the output signal VLO of the local oscillator (not shown) to an output terminal pair 6.
The IP2 controller 20 may include a first load resistor RLP, a second load resistor RLN and a calibration resistor RCAL. The calibration resistor RCAL may be coupled in parallel to the first load resistor RLP and/or the second load resistor RLN. The calibration resistor RCAL may compensate for a mismatch of the output terminal pair 6 of the mixer 10. The mixer 10 may output differential output signals VOP and VON. A total output voltage may be obtained by adding the output voltage of the IM2 from a common mode to the output voltage of the IM2 from a differential mode.
The output voltage VIM2,cm of the IM2 of the common mode may be represented byVIM2,cm=icm(R+ΔR−Rc)−icm(R−ΔR)=icm(2ΔR−Rc)  Equation 1where Rc may denote a resistance value offset by the calibration resistor RCAL, RLP may be equal to (R+ΔR) and RLN may be equal to (R−ΔR) and icm may denote an IM2 current in the common mode.
The output voltage VIM2,dm of the IM2 in the differential mode may be represented byVIM2,dm=idm(R+ΔR−Rc)+idm(R−ΔR)=idm(2R−Rc)  Equation 2where Rc may denote a resistance value offset by the calibration resistor RCAL, RLP may be equal to (R+ΔR), and RLN may be equal to (R−ΔR) and idm may denote an IM2 current in the differential mode.
The total IM2 output voltage VIM2 may be represented byVIM2=VIM2,cm+VIM2,dm=idm(2R−Rc)+icm(2ΔR−Rc)  Equation 3
Referring to Equation 3, the IP2 value may be calibrated by adjusting the resistance value Rc so as to reduce (e.g., minimize) the output voltage VIM2.
The above-described method of calibrating the IP2 value may cause difficulties in a semiconductor manufacturing process. For example, the ΔR may correspond to approximately 0.1%-10% of the resistance R, and the resistance value Rc may correspond to approximately 0.1%-10% of the resistance R. In order to implement such a broad range of the resistance value Rc, the calibration resistor RCAL may be set at a higher resistance value (e.g., between 10 and 1000 times higher than that of the resistance R). For example, if the resistance value of the resistor R is several tens of KΩ, the resistance value of the calibration resistor RCAL may be set at several tens of MΩ. Resistors with higher resistances may occupy higher amounts of space, thus complicating a manufacturing of semiconductors including the higher resistance resistors. Further, the IP2 calibration circuit 100 using the load resistors for calibrating the IP2 value may not have a sufficient voltage margin in a semiconductor device requiring a higher gain and/or a higher linearity.